1. Field of the Invention
The present invention relates to a signal line switching circuit, and more specifically to a signal line switching circuit in a semiconductor integrated circuit with a test circuit.
2. Description of Related Art
With a large scaling of semiconductor integrated circuits, a test for checking whether or not various circuits included in the integrated circuit can operate properly has become important. As one means for making the test easy in a large scaled integrated circuit such as a static random access memory (SRAM), many integrated circuits have incorporated therein a signal switching circuit for selecting either a data signal in a normal operation (called a "normal-data signal" hereinafter) or a test signal, in order to investigate existence/non-existence of failure before the integrated circuit is put in a normal operation condition.
In the prior art, this type of signal switching circuit has been used in sense amplifiers of the SRAM, and has been constituted of transfer gates or clocked inverters.
Referring to FIG. 1, there is shown a block diagram of a first example of the conventional signal switching circuit using a set of transfer gates. The shown first signal switching circuit includes a first stage amplifier A1 receiving a pair of complementary normal-data signals "a" and "Ia" having a small amplitude, and outputting a pair of amplified signals "b" and "Ib" on a pair of signal lines "B 1" and "B2". The first signal switching circuit also includes a switching circuit 1 responding to a pair of complementary normal-dam/test selection signals "m" and "Im" so as to select either the signals "b" and "Ib" or a pair of complementary test discrimination result signals "t" and "It" from a test circuit (not shown), and to output a pair of selected signals "c" and "Ic". Furthermore, the first signal switching circuit includes a second stage amplifier A2 receiving and amplifying the pair of selected signals "c" and "Ic" to output a pair of amplified signals "d" and "Id", and an output circuit 6 converting the pair of amplified signals "d" and "Id" into an output signal "e" of a predetermined signal type.
The switching circuit 1 includes a pair of NMOS (N-channel metal- oxide-semiconductor field effect) transistors N11 and N12 having their source connected to receive the signals "b" and "Ib", respectively, and their gate connected in common to receive the normal-data selection signal "m", and also their dram connected to supply the received signals "b" and "Ib" as the selected signals "c" and "Ic", respectively. The switching circuit 1 also includes another pair of NMOS transistors N13 and N14 having their source connected to receive the pair of test discrimination result signals "t" and "It", respectively, and their gate connected in common to receive the test selection signal "Im", and also their drain connected to supply the received signals "t" and "It" as the selected signals "c" and "Ic", respectively.
Now, operation of the first conventional signal switching circuit will be described with reference to FIG. 1. When the normal-data signal is to be outputted, the normal-data/test selection signals "m" and "Im" are set to a high level and to a low level, respectively. The pair of complementary normal-data signals "a" and "Ia" are amplified by the amplifier A1 so as to be outputted as the signals "b" and "Ib", respectively. In response to the normal-data selection signal "m" of the high level, the transistors N11 and N12 are put in a conductive condition, so that the signals "b" and "Ib" pass through the transistors N11 and N12 as they are, and are supplied to the amplifier A2 as the selected signals "c" and "Ic". On the other hand, in response to the test selection signal "Im" of the low level, the transistors N13 and N14 are put in a non-conductive condition, and therefore, the test discrimination result signals "t" and "It" are blocked, so that the signals "c" and "Ic" are not influenced by the test discrimination result signals "t" and "It" at all. The signals "c" and "Ic" are amplified by the amplifier A2, which outputs the amplified signals "d" and "Id" to the output circuit 6, which then supplies the output signal "e".
When the test discrimination result signal is to be outputted, the normal-data/test selection signals "m" and "Im" are set to a low level and to a high level, respectively, in the contrary to the case of outputting the normal-data signal. In response to the test selection signal "Im" of the high level, the transistors N13 and N14 are put in a conductive condition, so that the test discrimination result signals "t" and "It" pass through the transistors N13 and N14 as they are, and are supplied to the amplifier A2 as the selected signals "c" and "Ic". On the other hand, in response to the normal-data selection signal "m" of the low level, the transistors N11 and N12 are put in a non-conductive condition, and therefore, the amplified complementary normal-data signals "b" and "Ib" are blocked. As a result, the signals "c" and "Ic" corresponding to the test discrimination result signals "t" and "It" are amplified by the amplifier A2, which outputs the amplified signals "d" and "Id" to the output circuit 6, which then supplies the output signal "e". In this case, the output signal "e" is indicative of the test discrimination result signals "t" and "It".
Thus, the transistors N11 to N14 of the switching circuit 1 functions as the transfer gate controlled by the normal-data/test selection signals "m" and "Im".
Referring to FIG. 2, there is shown a block diagram of a second example of the conventional signal switching circuit using a set of clocked inverters. In FIG. 2, elements similar or corresponding to those shown in FIG. 1 are given the same Reference Numerals, and explanation thereof will be omitted for simplification of the description.
As seen from comparison between FIGS. 1 and 2, the second example of the conventional signal switching circuit is different from the first conventional signal switching circuit, in which a switching circuit 2 is provided which is constituted of a set of clocked inverters in place of the transfer gates of the switching circuit 1.
The switching circuit 2 includes a pair of clocked inverters I21 and I22 having their selection gate connected in common to receive the normal-data selection signal "m", and their input connected to receive the signals "b" and "Ib", respectively, and also their output for outputting the selected signals "c" and "Ic", respectively, and another pair of clocked inverters I23 and I24 having their selection gate connected in common to receive the test selection signal "Im", and their input connected to receive the test discrimination result signals "t" and "It", respectively, and also their output for outputting the selected signals "c" and "It", respectively,
Operation of the second conventional signal switching circuit is the same as that of the first conventional signal switching circuit, excepting that the selected signals "c" and "Ic" are either the inverted signals of the signals "b" and "Ib", respectively, or the inverted signals of the test discrimination result signals "t" and "It", respectively.
In the first conventional signal switching circuit as mentioned above, it is necessary to enlarge the size of the MOS transistors in order to reduce a conduction resistance and a junction capacitance which are causes for lowering the transmission speed of the signals passing through the MOS transistors put in a transmission path of the normal-data as the transfer gate. In addition, each of the test discrimination result signal and the normal-data/test selection signal is a pair of complementary signals, which correspondingly require a pair of signal lines. Therefore, the chip size has become large.
In the second conventional signal switching circuit as mentioned above, a signal delay corresponding to an inverter of at least one stage occurs because of the clocked inverters inserted in the transmission path of the normal-data. In addition, the number of transistors required for constituting the four clocked inverters is 16, and each of the test discrimination result signal and the normal-data/test selection signal requires a pair of complementary signal lines, similarly to the first conventional signal switching circuit. Accordingly, the chip size has become large, similarly to the first conventional signal switching circuit.